1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device having a shift-type redundant configuration.
2. Description of the Background Art
Recently, demand for semiconductor memory devices having high access speed and operating with low power consumption has been risen. As semiconductor memory devices which meet such demand, there is known a shift type semiconductor memory device.
As for the recent semiconductor memory devices which have been highly integrated, it is quite difficult to manufacture defect-free products. Therefore, redundant elements are provided in a semiconductor memory. device in advance, a defective part in which defect is generated in manufacturing processes is not used but a redundant element is used in place of the defective part, thereby improving yield.
However, the number of redundant elements is generally small in a shift type semiconductor memory device and there is a limit to the improvement of yield. In order to improve yield, therefore, a technique of increasing the number of redundant elements is disclosed in, for example, Japanese Patent Laying-Open No. 2000-100191 (hereinafter, referred to as “conventional technique”).
However, the conventional technique has a configuration in which a circuit for controlling a switching section which realizes shift type uses the result of the output signal of an adjacent circuit by propagating the result to the circuit. Therefore, it takes certain time to determine all shift states. In the case where a shift state is switched at real time for each access, access speed is disadvantageously decreased.
Further, according to the conventional technique, only two redundant elements for relieving defective parts are provided, which is insufficient to improve yield.